Introduction

The gate drive circuit is the interface between the control logic and the power stage, and it determines how an IGBT actually behaves in the system. A well-designed gate drive makes the difference between a robust converter and one that fails in the field from EMI, shoot-through or overvoltage. This application note explains the design of gate drive circuits for Firstack digital drivers, covering gate resistance, dead time, soft shutdown, active clamping and layout for high-voltage IGBT converters.

The Switching Physics in Brief

An IGBT turns on when its gate is charged above the threshold voltage, and it turns off when the gate is discharged. The gate resistor controls the charge and discharge current, which in turn controls the rate of voltage and current change at the switching transitions. A larger resistor slows the transitions, reducing EMI and voltage overshoot but increasing switching losses. A smaller resistor accelerates the transitions, reducing losses but increasing stress on the device and the system. The selection is therefore a trade-off, tuned to the application switching frequency and the EMI budget.

Gate Resistor Selection

Start with the module datasheet recommendation, then adjust on the bench: measure the collector voltage overshoot at turn-off, the EMI spectrum at the switching frequency and the device temperature. If the overshoot approaches the blocking voltage, increase the gate resistance; if the switching losses dominate the thermal budget, decrease it in small steps while monitoring the EMI. Separate turn-on and turn-off resistors are a common refinement, because turn-on and turn-off can be optimised independently: a slower turn-on controls the diode recovery di/dt, while a faster turn-off reduces tail losses.

Dead-Time Management

In a half bridge, both switches must never conduct together. The dead time between the turn-off of one device and the turn-on of the other must exceed the worst-case turn-off time plus the driver propagation delay, with margin. Too little dead time risks shoot-through and device failure; too much distorts the output waveform and reduces the available modulation. A digital driver makes the propagation delay consistent, which allows a tighter dead time with the same safety margin.

Protection: Soft Shutdown and Active Clamping

During a short circuit, turning the IGBT off as fast as normal would produce a large di/dt and a voltage spike that could destroy the device. Soft shutdown reduces the gate voltage slowly, so the fault current falls without an overvoltage spike. Active clamping then limits the turn-off peak by sensing the collector voltage and keeping the gate partly on through a controlled current source. At high voltage, where the spike grows with the bus and the loop inductance, active clamping is essential. Multi-level turn-off extends the idea by shaping the turn-off in stages.

Layout

Keep the gate loop short and the gate return close to the emitter, minimise the commutation loop formed by the DC-link capacitor and the switches, and keep the high-current path away from the low-level control signals. Measure overshoot at the module terminals, not at the bus, because the module sees the peak. The BeiLuo FAE team reviews gate drive and layout so the design reaches production with confidence.